1. Technical Field of the Invention
The present invention relates to a method and apparatus for writing directly into the memory cells of dynamic random access memory (DRAM) devices.
2. Background of the Invention
The core of a DRAM is typically partitioned into arrays or blocks of memory cells, with each array including a plurality of rows of memory cells, wherein the cells in each row are connected to a respective one of a plurality of word lines. Memory cells in each column of cells in an array are connected to a respective one of a plurality of bit lines.
A conventional DRAM memory block 100, as shown in FIG. 1, is based upon a single transistor architecture wherein the memory cell 105 comprises a storage capacitor 125 having a first terminal connected to a common reference node and a second terminal connected to a memory cell transmission gate, most often a transistor 120. The common reference node is typically connected to a voltage supply, generated on-chip, that is typically Vdd/2. Alternatively, the common reference node may be set to another voltage level, such as Vss.
The memory cell transistor 120 serves to transport charge to and from the storage capacitor 125 of the memory cell 105. The gate electrode of the memory cell transistor 120 is tied to a word line 115 decode signal, and the drain electrode thereof is connected to a bit line 112. Data is stored in the memory cell 105 as a charge on the storage capacitor 125. To select a particular memory cell 105, a word line 115 is electrically enabled by address data that is sent to the DRAM and decoded by row and column decoders (not shown).
A row of block (BLK) pass gates 130 is electrically coupled between the memory block 100 and a row of sense amplifiers 135. The BLK pass gates 130 are designed to electrically isolate the memory block 100 from the row of sense amplifiers 135 to reduce power and capacitive load when utilizing the sense amplifiers in the DRAM and to also serve as block switches when the sense amplifier is multiplexed between two memory blocks.
Sense amplifiers 135 are typically connected to the bit line pairs 110 of dynamic memory. The sense amplifier 135 is generally used in read and refresh operations to drive each bit line to a reference voltage level. When the dynamic memory is in the read and/or refresh mode, the sense amplifier 135 is used to sense the small difference in potential between the bit lines 112 in a bit line pair 110 following a connection of a memory cell to a bit line pair 110 and to drive each bit line 112, based upon the sensed voltage differential, to the appropriate full reference voltage level, such as Vdd or Vss. Once the sense amplifier 135 drives the bit lines 112 in the bit line pair 110 to opposite full reference voltage levels, the memory cell 105 from which data was read is refreshed with the appropriate full reference voltage signal. For example, if the memory cell 105 being accessed stores data (i.e., a data bit) representing a logic high value, then the sense amplifier 135 will drive bit line 112 substantially to the full Vdd level so that the full vdd level is stored in memory cell 105 upon the word line corresponding thereto being de-energized.
In a typical DRAM configuration, data bits to be written into the memory cells from external circuitry from the DRAM are transferred thereto via an external I/O bus (not shown). I/O data lines 145 are electrically connected between write drivers/read detectors 150 and I/O pass gates 155. The write drivers 150 are generally a byte or word long.
In prior DRAM designs, there are fewer write drivers/read detectors 150 than sense amplifiers 135. In order to write a full row of data a byte or word at a time into the memory block 100, a decoder (not shown) is incorporated into the DRAM. For example, if the DRAM were to have the number of I/O lines 145 being a byte wide (i.e., 8 inputs/8 outputs), 512 memory cells 105 in a row, and 512 sense amplifiers 135, then the ratio of sense amplifiers 135 to write drivers/read detectors 150 would be 512:8 or 64:1, thus requiring a 64:1 decoder. Each of a plurality of I/O enable lines 160 drives a byte or word wide set of I/O pass gates 155. Each decoder output drives a distinct I/O enable line 160 so that only one set of I/O pass gates 155 is activated (and corresponding bit line pairs 110 are driven) at a time.
An I/O ENABLE line 160, used to selectively turn "ON" and "OFF" the I/O pass gates 155, connects to the gate terminal of the transistor of each I/O pass gate 155. To write to and read from a selected memory cell 105, the external I/O bus connects to write drivers/read detectors 150. The write drivers 150 are connected to a sense amplifier 135 of the DRAM by I/O data lines 145.
A sense amplifier 135 can be viewed as cross-coupled inverters, which operates as a latch. Each sense amplifier 135 is connected to sense amplifier circuit 135 comprising switches that short the nodes of the sense amplifier 135 together and allow for precharging of the nodes to a reference voltage, such as Vdd/2, prior to a memory read or refresh operation. The sense amplifier circuit 135 also comprises switches SP and SN that turn-on and/or provide power to the sense amplifier 135 by connecting the common node of N-channel transistors to Vss and the common node of P-channel transistors to Vdd. Control lines SP 162 and SN 164 are connected to the gate nodes of switches SP and SN, respectively, and control the supply of power to the row of sense amplifiers 135. Configuration and operation of the sense amplifier 135 is well known in the art.
There exists equilibrate circuitry 165 in a conventional DRAM device that comprises a pair of transistors 185, a third transistor 190, an EQ line 170, a Vdd/2 line 175, and a node 180 that is electrically connected to the Vdd/2 line 175 and between the pair of transistors 185. The EQ line 170 is a control line that is connected to the gate terminals of the pair of transistors 185 and the third transistor 190. Each transistor of the pair of transistors 185 includes a first source/drain terminal connected to a distinct bit line 112 of the bit line pair 110 and a second source/drain terminal connected at the node 180 to the Vdd/2 line 175. The third transistor 190 is connected between the bit line pair 110.
Control circuitry 195 of a typical DRAM device is used to drive the control lines coupled to the various transmission gates to logic high and low voltage levels in order for the DRAM device to perform memory read, refresh, and write operations. For simplicity, the control and power circuitry 195 is shown as a block.
FIG. 2 is a timing diagram illustrating the execution of a traditional read-write operation for the traditional DRAM as presented in FIG. 1. A read cycle is performed immediately prior to a write cycle for the purpose of preventing the data within memory cells 105 in the selected row of memory cells that is not being written to by the write operation from being corrupted. To begin the read cycle, the power to the sense amplifiers 135 is turned off by control line signals SP 162 and SN 164 being set to logic high and low voltage levels, respectively. An equilibrate (EQ) signal 170 is driven to a logic high voltage level prior to or at the time T20. Responsive thereto, each bit line pair 110 and nodes within the row of sense amplifiers 135 are balanced and precharged to the same voltage level, typically Vdd/2. Once each bit line pair 110 and sense amplifiers 135 are precharged, the EQ signal 170 is transitioned to a logic low voltage at time T21.
Next, at time T22, a word line (WL) signal 115 is transitioned to a logic high voltage level to couple a desired row of memory cells 105 to the bit lines 112. A block (BLK) signal 140 is at a logic high voltage level during the read-write cycle so that the BLK pass gates 130 are "ON" and the sense amplifiers 135 are electrically coupled to the bit lines 112. At this time, a relatively slight charge and/or voltage differential exists between bit lines 112 of each bit line pair 110 due to the charge stored in the selected memory cells 105 being shared with one of the bit lines 112.
Just before time T23, the SP 162 signal and SN 164 signal are asserted to apply power to the row of sense amplifiers 135. Each sense amplifier 135, sensing the charge differential appearing across the bit line pair 110 associated therewith, drives the bit line pair 110 to opposite reference voltage levels (Vdd and Vss levels), based upon the charge bias provided by the corresponding memory cell storage capacitor 125. This is shown in FIG. 2 as the bit line signals 112 for a single bit line pair 110 are transitioned to logic high and low voltage levels at time T23.
At time T24, the I/O enable signal 160 transitions to a logic high voltage level so that the write drivers 150 can write data to the selected bit lines 112 to overpower the selected sense amplifiers 135. This new data is transferred through BLK pass gates 130 by the action of the sense amplifiers 135 being overwritten by the write drivers 150 through the I/O pass gates 155. This data value charges or discharges the bit lines 112 of the selected bit line pairs 110 to Vdd or to Vss, respectively. The voltage applied to the bit lines 112 allows charging or discharging of the storage capacitor 125 connected thereto. At time T25, the word line signal 115 is transitioned to a logic low voltage level so that each storage capacitor 125 in the row is again isolated from the bit lines 112. The I/O enable signal 160 may also be transitioned to a logic low voltage level at time T25 to turn OFF the I/O pass gates 155. To complete the read-write cycle of the traditional DRAM circuitry, the BLK signal 140 is transitioned to a logic low voltage level to isolate the row of sense amplifiers 135 from the memory block 100. At the end of the memory access cycle, the signals may be transitioned to the equilibrate states to prepare for the next memory access cycle as these cycles are continuous.
Writing in the above manner requires that the circuitry associated with driving the I/O data lines 145, such as the I/O pass gates 155 and the write drive circuitry 150, comprise low impedance devices because the sense amplifiers 135, being connected to the bit lines driven by the I/O circuitry, themselves drive the bit lines to voltage levels corresponding to a prior read operation. Low impedance I/O circuitry is therefore necessary to sufficiently overpower the sense amplifiers.
With regard to corrupting the data in the memory cells, by first reading and refreshing the entire row of memory cells 105 using the row of sense amplifiers 135, the memory cells 105 along the word line 115 that are not being written into do not become corrupt due to previously read data remaining in the sense amplifier 135 that was driving the bit line pair 110.
It would be a significant benefit to be able to bypass the sense amplifier and write directly into the bit line pairs while preserving data previously loaded on to the bit line pair from a row of memory cells in the sense amplifiers for later use.